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september 2006 hyb18tc1g800af hyb18tc1g160af 1-gbit ddr2 sdram ddr2 sdram rohs compliant internet data sheet rev. 1.11
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hyb18tc1g[80/16]0af 1-gbit ddr2 sdram qag_techdoc_rev400 / 3.2 qag / 2006-07-21 2 03292006-pjae-uqlg hyb18tc1g800af, hyb18tc1g160af revision history: 2006-09, rev. 1.11 page subjects (major chan ges since last revision) all qimonda update all adapted internet edition 102 modified ac timing parameters previous revision: 2006-07, rev. 1.1 added more speedsorts: hyb18tc1g800af-5, hyb18tc1g800af-3.7, hyb18tc1g800af-3s, hyb18tc1g160af-5, hyb18tc1g160af-3.7, hyb18tc1g160af-3s previous revision: 2005-07, rev. 1.0
internet data sheet rev. 1.11, 2006-09 3 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 1overview this chapter gives an overview of the 1-gbit double-dat a-rate-two sdram product family and describes its main characteristics. 1.1 features the 1-gbit double-data-rate sdram offers the following key features: ? 1.8 v 0.1 v power supply 1.8 v 0.1 v (sstl_18) compatible i/o ? dram organizations with 8, 16 data in/outputs ? double data rate architectu re: two data transfers per clock cycle four internal ban ks for concurrent operation ? cas latency: 3, 4, 5 ? burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differentia l data strobes (dqs and dqs ) are transmitted / received with da ta. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on- die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power- down modes ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? programmable self refres h rate via emrs2 setting ? dcc enabling via emrs2 setting ? full and reduced strengt h data-output drivers ? 1k page size for 8, 2k page size for 16 ? packages: pg-tfbga-68 for 8 components pg-tfbga- 92 for 16 components ? rohs compliant products 1) ? all speed grades faster than ddr400 comply with ddr2?400 timing specifications when run at a clock rate of 200 mhz. a list of the performance tables for the various speeds can be found below ? table 1 ?performance table for ?3s? on page 4 ? table 2 ?performance table for ?3.7? on page 4 ? table 3 ?performance table for ?5? on page 4 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers.
internet data sheet rev. 1.11, 2006-09 4 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 1 performance table for ?3s table 2 performance table for ?3.7 table 3 performance table for ?5 product type speed code ?3s unit speed grade ddr2?667d 5?5?5 ? max. clock frequency @cl5 f ck5 333 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns product type speed code ?3.7 unit speed grade ddr2?533c 4?4?4 ? max. clock frequency @cl5 f ck5 266 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns product type speed code ?5 unit speed grade ddr2?400b 3?3?3 ? max. clock frequency @cl5 f ck5 200 mhz @cl4 f ck4 200 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 40 ns min. row cycle time t rc 55 ns
internet data sheet rev. 1.11, 2006-09 5 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 1.2 description the 1-gb ddr2 dram is a high-speed double-data-rate- two cmos synchronous dram device containing 1,073,741,824 bits and internally configured as anoctal quad- bank dram. the 1-gb device is organized as either 16 mbit 8 i/o 8 banks or 8 mbit 16 i/o 8 banks chip. these synchronous devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. see table 1 to table 3 for performance figures. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency 2. write latency = read latency - 1 3. normal and weak strength data-output driver 4. off-chip driver (ocd) impedance adjustment 5. on-die termination (odt) function all of the control and address inputs are synchronized with a pair of externally supplied diff erential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 17 bit address bus for 4 and 8 organised components and a 16 bit address bus for 16 components is used to convey row, column and bank address information in aras - cas multiplexing style. the ddr2 device operates with a 1.8 v 0.1 v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in pg-tfbga package. table 4 ordering information for rohs compliant products note: for product nomenclature see chapter 9 of this data sheet product type org. speed cas-rcd-rp latencies 1)2)3) 1) cas: column address strobe 2) rcd: row column delay 3) rp: row precharge clock (mhz) package hyb18tc1g160bf?3s 16 ddr2?667d 5?5?5 333 pg?tfbga?92?1 hyb18tc1g800bf?3s 8 ddr2?667d 5?5?5 333 pg?tfbga?68?3 hyb18tc1g160bf?3.7 16 ddr2?533c 4?4?4 266 pg?tfbga?92?1 hyb18tc1g800bf?3.7 8 ddr2?533c 4?4?4 266 pg?tfbga?68?3 hyb18tc1g160bf?5 16 ddr2?400b 3?3?3 200 pg?tfbga?92?1 hyb18tc1g800bf?5 8 ddr2?400b 3?3?3 200 pg?tfbga?68?3
internet data sheet rev. 1.11, 2006-09 6 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 2 pin configuration this chapter contains the pin configuration. 2.1 pin configuration for tfbga?68 the pin configuration of a ddr2 sdram is listed by function in table 5 . the abbreviations used in the pin# and buffer type columns are explained in table 6 and table 7 respectively. the pin numbering for the fbga package is depicted in figure 1 for 8 components . table 5 pin configuration of ddr2 sdram ball#/pin# name pin type buffer type function clock signals 8 organizations j8 ck i sstl clock signal ck, complementary clock signal ck k8 ck i sstl k2 cke i sstl clock enable control signals 8 organizations k7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas i sstl k3 we i sstl l8 cs i sstl chip select address signals 8 organizations l2 ba0 i sstl bank address bus 2:0 l3 ba1 i sstl l1 ba2 i sstl m8 a0 i sstl address signal 12:0, address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl
internet data sheet rev. 1.11, 2006-09 7 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram r8 a13 i sstl address signal 13 note: 512 mbit 8 and 1 gbit 8 components nc ? ? note: 256 mbit data signals 8 organizations g8 dq0 i/o sstl data signal 3:0 note: dq[7:0] for 8 components g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl data signal 7:4 h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl data strobe 8 organizations f7 dqs i/o sstl data strobe e8 dqs i/o sstl data strobe 8 organizations f3 rdqs o sstl read data strobe e2 rdqs o sstl data mask 8 organizations f3 dm i sstl data mask power supplies 8 organizations e9,g1,g3,g7, g9 v ddq pwr ? i/o driver power supply e1,j9,m9,r1 v dd pwr ? power supply e7,f2,f8,h2,h 8 v ssq pwr ? i/o driver power supply e3,j3;n1,p9 v ss pwr ? power supply j2 v ref al ? i/o reference voltage j1 v ddl pwr ? power supply j7 v ssdl pwr ? power supply not connected 8 organization a1,a2,a8,a9,r 7,w1,w2,w8, w9,r3 nc nc ? not connected other pins 8 organizations k9 odt i sstl on-die termination control ball#/pin# name pin type buffer type function
internet data sheet rev. 1.11, 2006-09 8 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or.
internet data sheet rev. 1.11, 2006-09 9 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 1 pin configuration for 8 components, p-tfbga-68 (top view) notes 1. rdqs / rdqs are enabled by emrs(1) command. 2. if rdqs / rdqs is enabled, the dm function is disabled 3. when enabled, rdqs & rdqs are used as strobe signals during reads. 4. v ddl and v ssdl are power and ground for the dll. they are connected on the device from v dd , v ddq, v ss and v ssq . 0337 &6 %$ '4 '4 9 5() 18 5'46 $$3 $ $ $ $ $ $ 1& '4 '0 5'46 9 66 $ $ $ '4 '46 9 66'/ 9 664 9 ''4 9 664 $ 1& $ 9 ''4 '4 '4 '4 $ % & ' ) * + - ( / . 9 '' 9 664 9 ''4 '4 9 ''4 9 664 9 ''/ 9 66 &.( :( &. %$ 1&%$ 9 66 9 '' &$6 '46 9 ''4 9 664 &. 9 '' 5$6 2'7 9 '' $ 9 66 1&$ 0 1 3 5 7 8 9 : 1& 1& 1& 1& 1& 1& 1& 1&
internet data sheet rev. 1.11, 2006-09 10 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 2.2 pin configuration for tfbga-92 the pin configuration of a ddr2 s dram is listed by function in table 8 . the abbreviations used in the pin#/buffer type columns are explained in table 9 and table 10 respectively. the pin numbering for the fbga package is depicted in figure 2 for 16 components . table 8 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals 16 organization j8 ck i sstl clock signal ck, complementary clock signal ck k8 ck i sstl k2 cke i sstl clock enable control signals 16 organization k7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas i sstl k3 we i sstl l8 cs i sstl chip select address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 ba2 i sstl bank address bus 2 note: 1 gbit components and higher nc ? ? note: 256 mbit and 512 mbit components m8 a0 i sstl address signal 12:0,address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl
internet data sheet rev. 1.11, 2006-09 11 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram data signals 16 organization g8 dq0 i/o sstl data signal 15:0 note: bi-directional data bus. dq[15:0] for 16 components. g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data mask 16 organization b3 udm i sstl data mask upper byte f3 ldm i sstl data mask lower byte power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? power supply j7 v ssdl pwr ? power supply j3,n1,p9 v ss pwr ? power supply not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other pins 16 organization k9 odt i sstl on-die termination control ball#/pin# name pin type buffer type function
internet data sheet rev. 1.11, 2006-09 12 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 9 abbreviations for pin type table 10 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or.
internet data sheet rev. 1.11, 2006-09 13 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 2 pin configuration for 16 components, p-tfbga-92 (top view) notes 1. udqs/udqs is data strobe for upper byte, ldqs/ldqs is data strobe for lower byte 2. udm is the data mask si gnal for the upper byte udq0~udq7, ldm is the data mask signal for the lower byte ldq0~ldq7 0 3 3 7 & 6 % $ ' 4 $ $3 $ $ $ $ $ $ 1 & 9 6 6 $ $ $ ' 4 8 ' 4 6 9 6 6 ' / 9 6 6 4 9 ' ' 4 9 6 6 4 $ 1 & $ 9 ' ' 4 ' 4 ' 4 ' 4 $ % & ' ) * + - ( / . 9 ' ' 9 6 6 4 9 ' ' 4 ' 4 9 ' ' 4 : ( & . % $ % $ 9 6 6 9 ' ' & $6 8 ' 4 6 9 ' ' 4 9 6 6 4 & . 9 ' ' 5 $6 2 ' 7 9 ' ' $ 9 6 6 1 & 0 1 5 3 1 & 8 ' 0 1 & 9 6 6 ' 4 9 6 6 4 /' 0 9 ' ' 4 ' 4 9 ' ' 4 ' 4 9 6 6 4 ' 4 ' 4 9 6 6 4 ' 4 9 ' ' / 9 5 ( ) 9 6 6 & . ( 9 6 6 4 /' 4 6 9 ' ' 4 /' 4 6 9 6 6 4 ' 4 9 ' ' 4 ' 4 9 ' ' 4 ' 4 9 6 6 4 ' 4 9 ' ' 7 8 9 : ; $$ 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 &
internet data sheet rev. 1.11, 2006-09 14 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 3 functional description this chapter describes the functional description. table 11 mode register definition (ba[2:0] = 000b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 bank address ba1 15 bank address [1] 0 b ba1 bank address ba0 14 bank address [0] 0 b ba0 bank address a13 13 address bus[13] note: a13 is not available for 256 mbit and 16 512 mbit configuration 0 b a13 address bit 13 pd 12 w active power-down mode select 0 b pd fast exit 1 b pd slow exit wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 b wr 2 010 b wr 3 011 b wr 4 100 b wr 5 101 b wr 6 dll 8 w dll reset 0 b dll no 1 b dll yes tm 7 w test mode 0 b tm normal mode 1 b tm vendor specific test mode 0 3 % 7 % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3 ' : 5 % / u h j d g g u z z z z z z ' / / 7 0 & / % 7 z
internet data sheet rev. 1.11, 2006-09 15 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 12 extended mode register definition (ba[2:0] = 001b) cl [6:4] w cas latency note: all other bit combinations are illegal. 011 b cl 3 100 b cl 4 101 b cl 5 110 b cl 6 111 b cl 7 bt 3 w burst type 0 b bt sequential 1 b bt interleaved bl [2:0] w burst length note: all other bit combinations are illegal. 010 b bl 4 011 b bl 8 1) w = write only register bits 2) number of clock cycles for write recovery during auto- precharge. wr in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 bank address ba1 15 bank address [1] 0 b ba1 bank address ba0 14 bank address [0] 0 b ba0 bank address field bits type 1) description 0 3 % 7 % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4 r i i 5 ' 4 6 ' 4 6 2 & ' 3 u r j u d p 5 w w $/ 5 w w ' , & ' // u h j d g g u z z z z z z z z
internet data sheet rev. 1.11, 2006-09 16 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram a13 13 w address bus[13] note: a13 is not available for 256 mbit and 16 512 mbit configuration 0 b a13 address bit 13 qoff 12 output disable 0 b qoff output buffers enabled 1 b qoff output buffers disabled rdqs 11 read data strobe ou tput (rdqs, rdqs) 0 b rdqs disable 1 b rdqs enable dqs 10 complement data strobe (dqs output) 0 b dqs enable 1 b dqs disable ocd program [9:7] off-chip driver ca libration program 000 b ocd ocd calibration mode exit, maintain setting 001 b ocd drive (1) 010 b ocd drive (0) 100 b ocd adjust mode 111 b ocd ocd calibration default al [5:3] additive latency note: all other bit combinations are illegal. 000 b al 0 001 b al 1 010 b al 2 011 b al 3 100 b al 4 r tt 6,2 nominal termination resistance of odt note: see table 23 ?odt dc electrical characteristics? on page 24 00 b rtt (odt disabled) 01 b rtt 75 ohm 10 b rtt 150 ohm 11 b rtt 50 ohm dic 1 off-chip driver im pedance control 0 b dic full (driver size = 100%) 1 b dic reduced dll 0 dll enable 0 b dll enable 1 b dll disable 1) w = write only register bits field bits type 1) description
internet data sheet rev. 1.11, 2006-09 17 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 13 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 w bank address[2] note: ba2 is not available on 256 mbit and 512 mbit components 0 b ba2 bank address ba [15:14] w bank adress[15:14] 00 b ba mrs 01 b ba emrs(1) 10 b ba emrs(2) 11 b ba emrs(3): reserved a[13:7]w address bus[13:0] note: a13 is not available for 256 mbit and 16 512 mbit configuration 0 b a[13:0] address bits a7 w address bus[7], adapted self refresh rate for t case > 85 c 0 b a7 disable 1 b a7 enable 2) 2) when dram is operated at 85 c t case 95 c the extended self refresh rate must be enabled by setting bit a7 to "1" before the self refresh mode can be entered. a [6:4] w address bus[6:4] 0 b a[6:4] address bits a3 w address bus[3], duty cycle correction (dcc) 0 b a[3] dcc disabled 1 b a[3] dcc enabled partial self refresh for 8 banks a [2:0] w address bus[2:0], partial array self refresh for 8 banks 3) 000 b pasr0 full array 001 b pasr1 half array (ba[2:0]=000, 001, 010 & 011) 010 b pasr2 quarter array (ba[2:0]=000, 001) 011 b pasr3 1/8 array (ba[2:0] = 000) 100 b pasr4 3/4 array (ba[2:0]= 010, 011, 100, 101, 110 & 111) 101 b pasr5 half array (ba[2:0]=100, 101, 110 & 111) 110 b pasr6 quarter array (ba[2:0]= 110 & 111) 111 b pasr7 1/8 array(ba[2:0]=111) 3) if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if t ref conditions are met and no self refresh command is issued 03%7 %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu 65) '&& 3$65
internet data sheet rev. 1.11, 2006-09 18 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 14 emr(3) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 reg.addr bank address[2] note: ba2 is not available on 256 mbit and 512 mbit components 0 b ba2 bank address ba1 15 bank adress[1] 1 b ba1 bank address ba0 14 bank adress[0] 1 b ba0 bank address a [13:0] w address bus[13:0] note: a13 is not available for 256 mbit and 16 512 mbit configuration 0 b a[13:0] address bits 0 3 % 7 % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ u h j d g g u
internet data sheet rev. 1.11, 2006-09 19 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 15 odt truth table note: x = don?t care; 0 = bit set to low; 1 = bit set to high input pin emrs(1) address bit a10 emrs(1) address bit a11 8 components dq[7:0] x dqs x dqs 0x rdqs x 1 rdqs 01 dm x 0 16 components dq[7:0] x dq[15:8] x ldqs x ldqs 0x udqs x udqs 0x ldm x udm x
internet data sheet rev. 1.11, 2006-09 20 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 16 burst length and sequence notes 1. page size and length is a function of i/o organization:256 mb 4 organization (ca[9:0], ca11); page size = 1 kbyte; page length = 2048128 mb 8 organization (ca[9:0]); page size = 1 kbyte; page length = 102464 mb 16 organization (ca[9:0]); page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble- based? and therefore diff erent from sdr or ddr components burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
internet data sheet rev. 1.11, 2006-09 21 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 4 truth tables the truth tables in this chapter summar ize the commands and there signal coding to control a standard double-data-rate-two sdram. table 17 command truth table function cke cs ras cas we ba0 ba1 ba2 a[13:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas, and cke at the rising edge of the clock. 5) bank addresses ba[2:0] determine which bank is to be operated upon. for (e)mrs ba[2:0] selects an (extended) mode register. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)8) 8) burst reads or writes at bl = 4 cannot be terminated. write with auto- precharge hhlhllbacolumnhcolumn 4)5)8) read h h l h l h ba column l column 4)5)8) read with auto- precharge hhlhlhbacolumnhcolumn 4)5)8) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)9) 9) the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements. lh h h power down exit l h h x x x x x x x 4)9) lh h h
internet data sheet rev. 1.11, 2006-09 22 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 18 clock enable (cke) truth table for synchronous transitions table 19 data mask (dm) truth table current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2) 3) ras , cas , we 2) command (n) is the command registered at clock e dge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; c ke (n-1) was the state of cke at the previous clock edge. current cycle 6) (n) power-down l l x maintain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refre sh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown ar e illegal or reserved unless explicitly described else where in this document. 10) valid commands for power-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2x t cke + t ih . self refresh l l x maintain self refresh 8)11)12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 9)12)13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refresh exit are nop and deselct only. bank(s) active h l deselect or nop active power-down entry 7)9)10)11)15) 15) power-down and self refresh can not be entered while read or write operations, (extended) mode register operations, precharg e or refresh operations are in progress. all banks idle h l deselect or nop precharge power-down entry 9)10)11)15) h l autorefresh self refresh entry 7)11)14)16) 16) self refresh mode can only be entered from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x 1)
internet data sheet rev. 1.11, 2006-09 23 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 5 operating conditions this chapter lists the electrical characteristics and distinguishes between abolute maximum ratings, dc operating conditions and ac operating conditions. for i dd characteristics please see chapter 6 . 5.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 20 at any time. table 20 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 21 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit note min. max. t oper operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dr am specification will be suppor ted. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c tcase tem perature range, the high temperature self refresh has to be enable d by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%
internet data sheet rev. 1.11, 2006-09 24 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 5.2 dc characteristics this chapter describes the dc characteristics. table 22 recommended dc operating conditions (sstl_18) table 23 odt dc electrical characteristics table 24 input and output leakage currents symbol parameter rating unit note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1) v ddq supply voltage for output 1.7 1.8 1.9 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noi se margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . parameter / condition sym bol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i( v ihac ) and i( v ilac ) respectively. rtt(eff) = ( v ih(ac) ? v il(ac) ) /(i( v ihac ) ? i( v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 ? 1) termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 ? 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage ( v m ) at test pin (midpoint) with no load: delta v m = ((2 v m / v ddq )? 1) x 100% symbol parameter / condition min. max. unit note iil input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v iol output leakage current; 0 v < v out < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off
internet data sheet rev. 1.11, 2006-09 25 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system des ign. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these ti ming relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and characterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. table 25 dc & ac logic input levels table 26 single-ended ac input test conditions symbol parameter ddr2-400, ddr2-533 ddr2-667 unit min. max. min. max. v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v ref + 0.200 ? v v il(ac) ac input low ? v ref ? 0.250 ? v ref ? 0.200 v symbol condition value unit note v ref input reference voltage 0.5 v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 3 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions.
internet data sheet rev. 1.11, 2006-09 26 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 3 single-ended ac input test conditions diagram table 27 differential dc and ac in put and output logic levels symbol parameter min. max. unit note v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 x v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which differential input signals must cross. v ox(ac) ac differential cross po int output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 x v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which differential input signals must cross. 03(7 'howd75 'howd7) 9 6:,1*0$; 9 ''4 9 ,+df plq 9 ,+gf plq 9 5() 9 ,/gf pd[ 9 ,/df pd[ 9 66 5lvlqj6ohz 9 ,+df plq9 5() 'howd75 9 5() 9 ,/df pd[ )doolqj6ohz 'howd7)
internet data sheet rev. 1.11, 2006-09 27 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 4 differential dc and ac input and output logic levels diagram 5.4 output buffer characteristics this chapter describes the output buffer characteristics. table 28 sstl_18 output dc current drive table 29 sstl_18 output ac test conditions symbol parameter sstl_18 unit note i oh output minimum source dc current ?13.4 ma 1)2) 1) v ddq = 1.7 v; v out = 1.42 v. ( v out ? v ddq ) / i oh must be less than 21 ohm for values of v out between v ddq and v ddq ? 280 mv. 2) the values of i oh(dc) and i ol(dc) are based on the conditions given in 1) and 3) . they are used to test driv e current capability to ensure v ih.min . plus a noise margin and v il.max minus a noise margin are delivered to an sstl_18 rece iver. the actual current values are derived by shifting the desired driver operating points along 21 ohm lo ad line to define a convenient current for measurement. i ol output minimum sink dc current 13.4 ma 2)3) 3) v ddq = 1.7 v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. symbol parameter sstl_18 unit note v oh minimum required output pull-up v tt + 0.603 v 1) 1) sstl_18 test load for v oh and vol is different from the referenced load. the sstl_18 test load has a 20 ohm seri es resistor additionally to the 25 ohm termination resistor into v tt . the sstl_18 definition assumes that 335 mv must be developed across the effectively 25 ohm termination resistor (13.4 ma x 25 ohm = 335 mv). with an addi tional series resistor of 20 ohm this translates into a minim um requirement of 603 mv swing relative to v tt , at the ouput device (13.4 ma x 45 ohm = 603 mv). v ol maximum required output pull-down v tt ? 0.603 v 1) v otr output timing measurement reference level 0.5 v ddq v crossing point vddq vssq vid vix or vox vtr vcp sstl18_3
internet data sheet rev. 1.11, 2006-09 28 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 30 ocd default characteristics 5.5 input / output capacitance table 31 input / output capacitance symbol description min. nominal max. unit note ? output impedance ohms 1)2) 1) absolute specifications ( t oper ; v dd = 1.8 v 0.1 v; v ddq = 1.8 v 0.1 v), altering ocd from default state no longer requires dram to meet timing, voltage and slew rate specifications on i/o?s. 2) impedance measurement condition for output source dc current: v ddq = 1.7 v, v out = 1420 mv; ( v out ? v ddq ) / i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq ? 280 mv. impedance measurement condi tion for output sink dc current: v ddq = 1.7 v; v out = ?280 mv; v out / i ol must be less than 23.4 ohms for values of v out between 0 v and 280 mv. ? pull-up / pull down mismatch 0 ? 4 ohms 1)2)3) 3) mismatch is absolute value between pull-up and pull- down, both measured at same temperature and voltage. ? output impedance step size for ocd calibration 0 ? 1.5 ohms 4) 4) this represents the step size when the ocd is near 18 ohms at nominal conditions ac ross all process parameters and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. s out output slew rate 1.5 ? 5.0 v / ns 1)5)6)7)8) 5) slew rates according to v il(ac) to v ih(ac) . 6) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac t o ac. this is verified by design and characterization but not subject to production test. 7) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq?s is included in t dqsq and t qhs specification. 8) dram output slew rate specificati on applies to 400 and 533 speed bins. symbol parameter ddr2-400 & ddr- 2-533 ddr2-667 unit min. max. min. max. cck input capacitance, ck and ck 1.0 2.0 1.0 2.0 pf cdck input capacitance delta, ck and ck ? 0.25 ? 0.25 pf ci input capacitance, all other input-only pins 1.0 2.0 1.0 2.0 pf cdi input capacitance delta, all ot her input-only pins ? 0.25 ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs , rdqs, rdqs 2.5 4.0 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ? 0.5 ? 0.5 pf
internet data sheet rev. 1.11, 2006-09 29 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 5.6 overshoot and undershoot specification table 32 ac overshoot / undershoot specification for address and control pins figure 5 ac overshoot / undershoot diagram for address and control pins parameter ddr2-400 ddr2-533 dd2-667 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above v dd 1.33 1.00 0.80 v.ns maximum undershoot area below v ss 1.33 1.00 0.80 v.ns 9 ' ' 9 6 6 2 y h u v k r r w $u h d 8 q g h u v k r r w $u h d 0 d [ l p x p $p s o l w x g h 0 d [ l p x p $p s o l w x g h 7l p h q v 9 r o w v 9
internet data sheet rev. 1.11, 2006-09 30 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 33 ac overshoot / undershoot specification for clock, data, strobe and mask pins figure 6 ac overshoot / undershoot diagram for clock, data, strobe and mask pins parameter ddr2-400 ddr2-533 dd2-667 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.38 0.28 0.23 v.ns maximum undershoot area below v ssq 0.38 0.28 0.23 v.ns 9 ' ' 4 9 6 6 4 2 y h u v k r r w $u h d 8 q g h u v k r r w $u h d 0 d [ l p x p $p s o l w x g h 0 d [ l p x p $p s o l w x g h 7l p h q v 9 r o w v 9
internet data sheet rev. 1.11, 2006-09 31 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 6 currents specifications and conditions for double-data-rate-two sdrams described in this data sheet the maximum i dd values are listed in table 36 . the measurement conditions for i dd characteristics are listed in table 34 , general timing conditions used are listed in table 35 . at the end of this chapter the on-die-termination currents are defined. table 34 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switch ing; databus inputs are switching. i dd0 1)2)3)4)5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 1)2)3)4)5)6) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address inputs are stable; data bus inputs are floating . i dd2p 1)2)3)4)5)6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n 1)2)3)4)5)6) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and a ddress inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) 1)2)3)4)5)6) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd3n 1)2)3)4)5)6) operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4)5)6) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4)5)6) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b 1)2)3)4)5)6)
internet data sheet rev. 1.11, 2006-09 32 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 35 definition for i dd distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d 1)2)3)4)5)6) self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 1)2)3)4)5)6) operating bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; t faw = t faw(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. 2. timing pattern for x4 and x8 components: ddr2-400: a0 ra0 a1 ra1 a2 ra2 a3 ra3 a4 ra4 a5 ra5 a6 ra6 a7 ra7 (16 clocks) ddr2-533: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d (20 clocks) timing pattern for x16 components: ddr2-400: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d ( 20 clocks) ddr2-533: a0 ra0 a1 ra1 a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d (26 clocks) i dd7 1)2)3)4)5)6)7) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : see table 35 6) timing parameter minimum and maximum values for i dd current measurements are defined in table 46. 7) a = activate, ra = read with auto-precharge, d=deselect parameter description low defined as v in v il(ac).max high defined as v in v ih(ac).min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer(once per clock) for dq signals not including mask or strobes parameter symbol note
internet data sheet rev. 1.11, 2006-09 33 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 36 i dd specification for hyb18tc1g[80/16]0af symbol ?3s ?3.7 -5 unit note ddr2?667d ddr2?533c ddr2 - 400b i dd0 81 75 70 ma 8 90 80 75 ma 16 i dd1 100 85 80 ma 8 109 95 90 ma 16 i dd2n 60 29 35 ma i dd2p 777ma i dd2q 39 23 28 ma i dd3n 65 50 40 ma i dd3p 22 14 18 ma 1) 1) mrs(12)=0 969ma 2) 2) mrs(12)=1 i dd4r 200 145 115 ma 8 240 175 140 ma 16 i dd4w 200 140 110 ma 8 260 195 155 ma 16 i dd5b 200 185 180 ma i dd5d 10 10 10 ma 3) 3) for i dd5d and i dd6 : 0 t case 85 c i dd6 888ma i dd7 242 230 205 ma 8 313 300 265 ma 16
internet data sheet rev. 1.11, 2006-09 34 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 7 timing characteristics this chapter contains speed grade definition, ac timing parameter and odt tables. 7.1 speed grade definitions all speed grades faster than ddr2-ddr400b comply with ddr2-ddr400b timing specifications ( t ck = 5ns with t ras = 40ns). list of speed grade definition tables: ? table 37 ?speed grade definition speed bins for ddr2?667d? on page 34 ? table 38 ?speed grade definition speed bins for ddr2?533c? on page 35 ? table 39 ?speed grade definition speed bins for ddr2?400b? on page 36 table 37 speed grade definition speed bins for ddr2?667d speed grade ddr2?667d unit note ifx sort name ?3s cas-rcd-rp latencies 5?5?5 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode.timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements? . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/c k, dqs / dqs, rdqs / rdqs is defined. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 38ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4)
internet data sheet rev. 1.11, 2006-09 35 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 38 speed grade definition speed bins for ddr2?533c speed grade ddr2?533c unit note ifx sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements?. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/c k, dqs / dqs, rdqs / rdqs is defined. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4)
internet data sheet rev. 1.11, 2006-09 36 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 39 speed grade definition speed bins for ddr2?400b speed grade ddr2?400b unit note ifx sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0). 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 58 ns 1)2)3)4) @ cl = 5 t ck 58 ns 1)2)3)4) row active time t ras 40 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 t refi . row cycle time t rc 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4)
internet data sheet rev. 1.11, 2006-09 37 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 7.2 ac timing parameters list of timing parameters tables. ? table 40 ?timing parameter by speed grade - ddr2?667? on page 37 ? table 41 ?timing parameter by speed grade - ddr2?533? on page 42 ? table 42 ?timing parameter by speed grade - ddr2-400? on page 44 table 40 timing parameter by speed grade - ddr2?667 parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) min. max. dq output access time from ck / ck t ac ?450 +450 ps 8) dqs output access time from ck / ck t dqsck ?400 +400 ps 8) average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 9)10) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 9)10) average clock period t ck.avg 3000 8000 ps dq and dm input setup time t ds.base 100 ? ps 11)12)13) dq and dm input hold time t dh.base 175 ? ps 12)13)14) control & address input pulse width for each input t ipw 0.6 ? t ck.avg dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg data-out high-impedance time from ck / ck t hz ? t ac.max ps 8)15) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 8)15) dq low impedance time from ck/ck t lz.dq 2 t ac.min t ac.max ps 8)15) dqs-dq skew for dqs & associated dq signals t dqsq ? 240 ps 16) ck half pulse width t hp min( t ch.abs , t cl.abs ) ?ps 17) dq hold skew factor t qhs ? 340 ps 18) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 19) write command to dqs associated clock edges wl rl?1 nck dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 20) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 20) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 20) write postamble t wpst 0.4 0.6 t ck.avg write preamble t wpre 0.35 ? t ck.avg address and control input setup time t ls.base 200 ? ps 21)22) address and control input hold time t lh.base 275 ? ps 22)23) read preamble t rpre 0.9 1.1 t ck.avg 24)25) read postamble t rpst 0.4 0.6 t ck.avg 24)26) active to precharge command t ras 45 70000 ns 27)
internet data sheet rev. 1.11, 2006-09 38 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram active to active command period for 1kb page size products t rrd 7.5 ? ns 27) active to active command period for 2kb page size products t rrd 10 ? ns 27) four activate window for 1kb page size products t faw 37.5 ? ns 27) four activate window for 2kb page size products t faw 50 ? ns 27) cas to cas command delay t ccd 2?nck write recovery time t wr 15 ? ns 27) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 28)29) internal write to read command delay t wtr 7.5 ? ns 27)30) internal read to precharge command delay t rtp 7.5 ? ns 27) exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 27) exit self-refresh to read command t xsrd 200 ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? nck cke minimum pulse width ( high and low pulse width) t cke 3?nck 31) odt turn-on delay t aond 22nck odt turn-on t aon t ac.min t ac.max +0.7 ns 8)32) odt turn-on (power down mode) t aonpd t ac.min +2 2 t ck.avg + t ac.max +1 ns odt turn-off delay t aofd 2.5 2.5 nck odt turn-off t aof t ac.min t ac.max +0.6 ns 33)34) odt turn-off (power down mode) t aofpd t ac.min + 2 2.5 t ck.avg + t ac.max +1 ns odt to power down entry latency t anpd 3?nck odt to power down exit latency t axpd 8?nck mode register set command cycle time t mrd 2?nck mrs command to odt update delay t mod 012ns 28) ocd drive mode output delay t oit 012ns 28) minimum time clocks remain on after cke asynchronously drops low t delay t ls + t ck .avg + t lh ?ns 1) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) min. max.
internet data sheet rev. 1.11, 2006-09 39 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 6) the output timing reference voltage level is v tt . 7) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 8) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 9) input clock jitter spec parameter. these parameters are referr ed to as 'input clock jitter s pec parameters' and these paramet ers apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 10) these parameters are specified per their average values, howe ver it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations). 11) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appl ied to the device under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see differential input waveform timing - tds and tds. 12) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 13) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 14) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refer enced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see differential input waveform timing - tds and tds. 15) t hz and t lz transitions occur in the same access time as valid data tran sitions. these parameters are referenced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 16) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 17) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 18) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to da ta pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 19) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse widt h distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 20) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 21) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see differential input waveform timing - tls and tlh. 22) these parameters are measured from a comm and/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 23) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see differential input waveform timing - tls and tlh. 24) t rpst end point and t rpre begin point are not referenced to a specific voltage le vel but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). method for calculating transitions and endpoint show s a method to calculate these points when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent.
internet data sheet rev. 1.11, 2006-09 40 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 25) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 26) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 27) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all inpu t clock jitter specifications are met. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input clock jitter specificati ons are met, precharge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 28) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 29) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 30) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. 31) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 32) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond . 33) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . 34) when the device is operated with input clock jitter, this parameter needs to be derated by {? t jit.duty.max ? t err(6-10per).max } and {? t jit.duty.min ? t err(6-10per).min } of the actual input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps, t err(6- 10per).max = + 293 ps, t jit.duty.min = ? 106 ps and t jit.duty.max = + 94 ps, then t aof.min(derated) = t aof.min + {? t jit.duty.max ? t err(6-10per).max } = ? 450 ps + {? 94 ps ? 293 ps} = ? 837 ps and t aof.max(derated) = t aof.max + {? t jit.duty.min ? t err(6-10per).min } = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (caution on the min/max usage!)
internet data sheet rev. 1.11, 2006-09 41 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 7 method for calculating transitions and endpoint figure 8 differential input waveform timing - t ds and t ds figure 9 differential input waveform timing - t ls and t lh thz trpst end point t1 t2 voh - x mv voh - 2x mv vol + 2x mv vol + x mv tlz trpre begin point t2 t1 vtt + 2x mv vtt + x mv vtt - x mv vtt - 2x mv tlz,trpre begin point = 2*t1-t2 thz,trpst end point = 2*t1-t2 w' 6 9 '' 4 9 ,+d f pl q 9 ,+g f pl q 9 5()gf 9 ,/ g f pd [ 9 ,/ d f pd [ 9 66 '4 6 '46 w'+ w'6 w'+ tis v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss ck ck tih tis tih
internet data sheet rev. 1.11, 2006-09 42 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 41 timing parameter by speed grade - ddr2?533 parameter symbol ddr2?533 unit note 1)2)3)4)5)6) min. max. dq output access time from ck / ck t ac ?500 +500 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 7)17) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns 8) dq and dm input hold time (differential data strobe) t dh (base) 225 ? ps 9) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 10) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 10) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 10) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 10) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck four activate window period t faw 37.5 ? ns 50 ? ns 12) clock half period t hp min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ps 12) address and control input hold time t ih (base) 375 ? ps 10) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps 10) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 13) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 13) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ?
internet data sheet rev. 1.11, 2006-09 43 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram data hold skew factor t qhs ? 400 ps average periodic refresh interval t refi ?7.8 s 13)14) ?3.9 s 15)17) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 16) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 13) read postamble t rpst 0.40 0.60 t ck 13) active bank a to active bank b command period t rrd 7.5 ? ns 13)17) 10 ? ns 15)19) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 19) internal write to read command delay t wtr 7.5 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 21) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) for timing definition, refer to the component data sheet. 10) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). parameter symbol ddr2?533 unit note 1)2)3)4)5)6) min. max.
internet data sheet rev. 1.11, 2006-09 44 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 42 timing parameter by speed grade - ddr2-400 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the devic e output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 17) the t rrd timing parameter depends on the page size of the dram organization. see table 4 ?ordering information for rohs compliant products? on page 5 . 18) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ddr2?400 unit note 1)2)3)4)5)6) min. max. dq output access time from ck / ck t ac ?600 +600 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 7)21) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns 8) dq and dm input hold time (differential data strobe) t dh (base) 275 ? ps 9) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 10) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?500 + 500 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps 10) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 150 ? ps 10) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 10)
internet data sheet rev. 1.11, 2006-09 45 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck four activate window period t faw 37.5 ? ns 50 ? ns 12) clock half period t hp min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ps 12) address and control input hold time t ih (base) 475 ? ps 10) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 350 ? ps 10) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 13) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 13) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ?? data hold skew factor t qhs ? 450 ps average periodic refresh interval t refi ?7.8 s 13)14) ? 3.9 s 15)17) auto-refresh to active/auto-refresh command period 127.5 ? ns 16) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 13) read postamble t rpst 0.40 0.60 t ck 13) active bank a to active bank b command period t rrd 7.5 ? ns 13)17) 10 ? ns 15)19) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 t ck ? t ck write postamble t wpst 0.40 0.60 t ck 18) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 19) internal write to read command delay t wtr 10 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 21) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck parameter symbol ddr2?400 unit note 1)2)3)4)5)6) min. max.
internet data sheet rev. 1.11, 2006-09 46 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) for timing definition, refer to the component data sheet. 10) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the devic e output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 17) the t rrd timing parameter depends on the page size of the dram organization. see table 4 ?ordering information for rohs compliant products? on page 5 . 18) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ddr2?400 unit note 1)2)3)4)5)6) min. max.
internet data sheet rev. 1.11, 2006-09 47 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 7.3 odt ac electrical characteristics this chapter describes the odt ac electrical characteristics. table 43 odt ac characteristics and operating conditions for ddr2-667 table 44 odt ac characteristics and operating conditions for ddr2-533/ddr2-400 symbol parameter / cond ition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 0.7 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (pow er-down modes) t ac.min +2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (p ower-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck symbol parameter / cond ition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (pow er-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (p ower-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
internet data sheet rev. 1.11, 2006-09 48 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 8 package dimensions the 1-gbit ddr2 sdram is sold in two different packages depending on the number of i/os. figure 10 package outline pg-tfbga-68 [ % $ 0 $; 0 , 1 6 ( $ 7 , 1 * 3 /$1 ( & % ? ? [ ? ? & 0 0 $ ' x p p \ s d g v z l w k r x w e d o o 3 d f n d j h r u l h q w d w l r q p d u n $ % d g x q l w p d u n l q j % 8 0 0 l g g o h r i s d f n d j h v h g j h v ' l h v r uw i l g x f l d o [ 0 $; & & 0 $;
internet data sheet rev. 1.11, 2006-09 49 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 11 package pinout p-tfbga-92 (top view) [ $ % ? ? ? 0 ? [ 0 & $ % & 6 ( $ 7, 1 * 3 /$1 ( 0 l g g o h r i s d f n d j h v h g j h v % d g x q l w p d u n l q j % 8 0 3 d f n d j h r u l h q w d w l r q p d u n $ ' x p p \ s d g v z l w k r x w e d o o [ 0 $; & & 0 , 1 0 $; 0 $; ' l h v r u w i l g x f l d o
internet data sheet rev. 1.11, 2006-09 50 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 9 product nomenclature for reference the qimonda sdram component nomenclature is enclosed in this chapter. table 45 nomenclature fields and examples table 46 ddr2 memory components example for field number 1234567891011 ddr2 dram hyb 18 tc 1gc 16 0 a c ?3.7 field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology, consumer variant tc ddr2 4 component density [mbit] 256 256 m 512 512 m 1g 1 gb 5+6 number of i/os 40 x4 80 x8 16 x16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?2.5 ddr2?800 6?6?6 ?3 ddr2?667 4?4?4 ?3s ddr2?667 5?5?5 ?3.7 ddr2?533 4?4?4 ?5 ddr2?400 3?3?3 11 n/a for components
internet data sheet rev. 1.11, 2006-09 51 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram figure 1 pin configuration for 8 components, p-tfbga-68 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 pin configuration for 16 components, p-tfbga-92 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3 single-ended ac input test conditions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4 differential dc and ac input and output logic levels diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5 ac overshoot / undershoot diagram for address and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6 ac overshoot / undershoot diagram for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7 method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 8 differential in put waveform timing - t ds and t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 9 differential in put waveform timing - t ls and t lh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 10 package outline pg-tfbga-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 11 package pinout p-tfbga-92 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 list of figures
internet data sheet rev. 1.11, 2006-09 52 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram table 1 performance table for ?3s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 performance table for ?3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3 performance table for ?5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 4 ordering information for rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 5 pin configuration of ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 6 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 8 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11 mode register definition (ba[2:0] = 000b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12 extended mode register definition (ba[2:0] = 001b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13 emrs(2) programming extended m ode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14 emr(3) programming extended m ode register defi nition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 15 odt truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 16 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 17 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 18 clock enable (cke) truth table for synchronous transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 19 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 20 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 21 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 22 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 23 odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 24 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 25 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 26 single-ended ac input test condition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 27 differential dc and ac input and output logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28 sstl_18 output dc current drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 29 sstl_18 output ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 30 ocd default characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 31 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 32 ac overshoot / undershoot specification for address and co ntrol pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 33 ac overshoot / undershoot specification for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . 30 table 34 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 35 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 36 i dd specification for hyb18tc1g[80/16]0af . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 37 speed grade definition speed bins for ddr2?667d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 38 speed grade definition speed bins for ddr2?533c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 39 speed grade definition speed bins for ddr2?400b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 40 timing parameter by speed grade - ddr2?667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 41 timing parameter by speed grade - ddr2?533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 42 timing parameter by speed grade - ddr2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 43 odt ac characteristics and operating conditions for ddr2-667. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 44 odt ac characteristics and operating conditions for ddr2-533/ddr2-400. . . . . . . . . . . . . . . . . . . . . . . . . 47 table 45 nomenclature fields and examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 46 ddr2 memory components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 list of tables
internet data sheet rev. 1.11, 2006-09 53 03292006-pjae-uqlg hyb18tc1g[80/16]0af 1-gbit ddr2 sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin configuration for tfbga?68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pin configuration for tfbga-92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 currents specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 product nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table of contents
edition 2006-09 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2006. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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